Semiconductor memory device for reducing cell area

摘要

Disclosed is a semiconductor memory device with a reduced cell area and a high-speed data transfer by modifying a circuit layout. The semiconductor memory device includes: a cell area with a first and a second cell areas, wherein each cell area is provided with a plurality of cell blocks and a plurality of bit line sense amplifying units; a plurality of Y decoders of which one Y decoder selects bit line sense amplifiers in the first and the second cell areas; IO sense amplifiers provided with a first IO sense amplifier and a second IO sense amplifier, wherein the first IO sense amplifier is disposed at one side of the cell area and the second IO sense amplifier is disposed at the other side of the cell area; a plurality of first data lines for transferring a data sensed and amplified at the bit line sense amplifier of the first cell area; and a plurality of second data lines for transferring a data sensed and amplified at the bit line sense amplifier of the second cell area.