| 摘要 |
PROBLEM TO BE SOLVED: To automatically and easily create an effective output expected value waveform even when a function (input mode) is selectively designated at optional timing. SOLUTION: In a step S1, a pattern file, which includes information about a waveform pattern of an output expected value for each area of the same operation mode serving as a factor and information showing a functions capable of transition in this operation mode, and a pattern selection management file for sequentially selecting the pattern file are registered. In a step S2, a function (input mode) sequentially switched to be selected as an input to a logic circuit is designated. In a step S3, the pattern file is sequentially selected according to the pattern selection management file matching the selectively designated function, and an output expected value waveform is created while determining a transitable function in the operation mode. In a step S4, the generated output expected value waveform and the output waveform acquired by the designated logic circuit simulation are compared with each other for performing verification. COPYRIGHT: (C)2006,JPO&NCIPI
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