Integrated memory circuit has error recognition unit with compression memory unit for bitline values and error data comparison unit

摘要

An integrated memory circuit comprises memory cells (3) in wordline (WL) and bitline (BL) array (2) with an error recognition circuit (5) to store and read cell data along a wordline, test against given data and generate error data. An adjusting unit (10) stores a compressed value and an error data unit (9) gives total error data for each bitline. An independent claim is also included for an error compression process as above.