| 摘要 |
A data transferring system comprises a host controller including an ATA bus host interface, a first data storage device, a second data storage device, and a switch. The switch directs a set of host chip-selection signals from the ATA bus host interface to a first set of chip-selection signal or to a second set of chip-selection signal, and these connect to the first and the second data storage device. When the processing priority of the second data storage device is higher than the processing priority of the first data storage device, when the host controller does not assert the chip-selection signals, and when the data storage device is not in the direct memory access (DMA) mode, the host controller controls the switch to connect to another set of chip-selection signals according to a channel selection signal after the host controller issues a first command to the first data storage device. Such arrangement enables the host controller to issue a second command to the second data storage device without interrupting or changing the command state of the first data storage device before the first command to the first data storage device is completed.
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