发明名称 |
Method of modulating a clock signal for digital circuits and clock modulator for carrying out said method |
摘要 |
The method varying the interval between adjacent switching edges by passing the base clock via a changing number of delay units (D1-D7). The delay times of the delay units are calibrated and each delay units has several delay elements that are switched in or switched out individually and/or in groups. An Independent claim is also included for a clock modulator. |
申请公布号 |
EP1071208(B1) |
申请公布日期 |
2005.11.09 |
申请号 |
EP20000114213 |
申请日期 |
2000.07.03 |
申请人 |
SIEMENS AKTIENGESELLSCHAFT;FUJITSU MICROELECTRONICS EUROPE GMBH |
发明人 |
SATTLER, FRANK, DR.;KLUMB, WALTER |
分类号 |
H03K5/06;G06F1/10;H03K5/13;H04B15/04 |
主分类号 |
H03K5/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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