| 摘要 |
A pixel modulation apparatus for converting pixel data D composed of N 1 bits to a pixel data signal composed of one bit. The pixel data D is input into the apparatus at a pixel period T 0 . The apparatus includes a first data conversion unit which converts the pixel data D to pixel data D 1 expanded to N 2 bits (N 2 >N 1 ) at the period T 0 , a second data conversion unit which converts the pixel data D 1 to pixel data D 2 composed of N 3 /m bits at a period T 0 /m, a third data conversion unit which inputs n data from among the pixel data D 2 and pixel data Dd 2 constituting the pixel data D 2 before having the period T 0 /m to execute logical sum operations a predetermined number (equal to or less than n) of times to convert the n data to pixel data D 3 composed of N 3 bits, including additional data corresponding to the predetermined number, and a fourth data conversion unit which converts the pixel data D 3 to the pixel data signal composed of one bit at the period T 0 /m.
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