发明名称 |
DEVICE, METHOD, AND PROGRAM FOR DESIGNING SUBSTRATE |
摘要 |
PROBLEM TO BE SOLVED: To make a loop check on circuit constitution of an arbitrary internal layer of a multi-layered substrate. SOLUTION: A loop check circuit 5 judges whether or not a loop circuit is present as to all layers present in the stage where a specified layer is manufactured. A wiring guide part 6 guides wires around components (DUT) forming a loop circuit to avoid forming the loop circuit when the loop circuit is present in all layers present at the stage where the specified layer is manufactured. A presentation control part 8 specifies the guided result to the designer and urges an operator to decide whether or not the guided result is reflected on a wiring pattern. A guide wire processing part 7 reflects the guided result on the wiring pattern when the operator agrees with the guided result. COPYRIGHT: (C)2006,JPO&NCIPI |
申请公布号 |
JP2005309729(A) |
申请公布日期 |
2005.11.04 |
申请号 |
JP20040125439 |
申请日期 |
2004.04.21 |
申请人 |
TOPPAN PRINTING CO LTD |
发明人 |
SAKAI TAKEJI |
分类号 |
G06F17/50;H05K3/00;H05K3/46;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|