| 摘要 |
A description of signal behavior in the vicinity of a time and voltage of interest is produced by defining a region in the (time, voltage) plane that is a closed straight sided figure whose vertices are identified by threshold crossings offset for the voltage of interest and clocked by time delays offset from a clock time of interest. A first set of latches clocked by the time delays accumulates the state of signal behavior relative to the threshold voltages as it occurs, and their contents are subsequently transferred to a second set of latches at the start of a new clock cycle, allowing a new accumulation to begin and also allowing a detection logic circuit to operate on a unified and completed collection of indicators of what the just concluded description amounts to. The detection logic circuit responds to the combinations of latched indications to produce a signal corresponding to that description. The closed figure need not be a rectangle, and it may also serve as an indication that a signal went into a region that it should not have, e.g., an eye violation detector.
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