SEMICONDUCTOR MEMORY DEVICE

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of guaranteeing a fast operation while increasing soft error resistance.

SOLUTION: This semiconductor memory device includes an SRAM memory cell formed on an SOI substrate. Inverters INV1 and INV2 include p type load transistors TP1 and TP2 whose sources are connected to a high potential power supply line VDD, n type driving transistors TN1 and TN2 whose sources are connected to a low potential power supply line VSS, and n type resistance added transistors TD1 and TD2 whose sources and drains are connected between storage nodes N1 and N2 and driving transistors TN1 and TN2 and whose gates are connected to a word line WL. In each of the resistance added transistors TD1 and TD2, a conductive state is set between the source and the drain when a gate voltage is the power supply voltage Vss of a low potential side.

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