| 摘要 |
In charging a gate of a NMOS transistor Q 1 , the charging speed is adjustable by varying a resistor R 1 . When an inputted pulse signal VIN reverses to a negative voltage, a diode D 2 turns off. Then, current flows along a discharging loop formed by the gate capacitor, the resistor R 1 , the emitter of the transistor Q 2 , the base of the transistor Q 2 , the resistor R 2 and the capacitor C 1 , the transformer T 1 and the source of the NMOS transistor Q 1 . A reverse bias voltage is applied to the gate of the NMOS transistor Q 1 , thereby keeping the NMOS transistor Q 1 off-state stably.
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