发明名称 CIRCUIT SUBSTRATE AND REDUCING METHOD OF NOISE THEREIN
摘要 PROBLEM TO BE SOLVED: To provide a circuit substrate in which via-holes for reducing high-frequency noise higher in noise reducing effect are formed instead of a conventional high-frequency noise reducing method for forming slits on a ground pattern. SOLUTION: The circuit substrate is provided with at least a ground layer on which a ground pattern is formed, an insulating layer, a wiring layer on which a wiring pattern is formed. These elements are laminated sequentially, and a circuit component is arranged on the wiring layer. A ground part separated from the ground pattern is formed around the circuit component on the wiring layer differently from the wiring pattern, and via-holes conduct the ground part with the ground pattern through the insulating layer. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2005294528(A) 申请公布日期 2005.10.20
申请号 JP20040107496 申请日期 2004.03.31
申请人 SEIKO EPSON CORP 发明人 NAKAYAMA TERUO
分类号 H05K9/00;H05K1/02;H05K3/46;(IPC1-7):H05K9/00 主分类号 H05K9/00
代理机构 代理人
主权项
地址