发明名称 Three-dimensional interconnect resistance extraction using variational method
摘要 A method and apparatus calculate resistance of a three-dimensional conductor system defined by boundary faces. The resistance calculation includes (a) partitioning the three-dimensional shape into a plurality of parallelepipeds, a boundary between two parallelepipeds forms and entire face for both of the two parallelepipeds, (b) determining at least one source face and at least one sink face from among the boundary faces, a current entering the conductor system through the source face and leaving the conductor system through the sink face, (c) setting boundary conditions with respect to the current for each of the parallelepipeds, (d) calculating power for each of the parallelepipeds with the boundary conditions, (e) calculating power for the conductor system based on the power and the boundary conditions of each of the parallelepipeds, and (f) obtaining the resistance of the conductor system by minimizing dissipation of the calculated power of the conductor system.
申请公布号 US2005235235(A1) 申请公布日期 2005.10.20
申请号 US20050032720 申请日期 2005.01.10
申请人 LSI LOGIC CORPORATION, A DELAWARE CORPORATION 发明人 DONIGER KENNETH
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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