FRAME BUFFER MANAGEMENT CIRCUIT AND METHOD

摘要

PROBLEM TO BE SOLVED: To provide a frame buffer management circuit for accelerating and improving efficiency in managing a memory shared individual FIFO type buffer which realizes fair reading of a variable length frame in the quantity of bands to be used and a delay time, rather than managing components in a link structure.

SOLUTION: There are included a frame distribution section for determining a buffer of a distribution destination for an inputted frame; a frame storage section; a memory block address management section for buffer for instructing memory block using a pointer; a queue management section for instructing the top and end positions of the buffer using a pointer; an empty memory block management section for instructing a non-used memory block using a pointer; a frame length management section for holding a length of a frame to be accommodated; a storage/read/discard discrimination section for discriminating which operation is to be executed; a frame reading section for reading a frame from the frame storage means; and a frame discarding section for discarding frames if all the frames can not be stored.

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