发明名称 |
Multiple-capture DFT system for scan-based integrated circuits |
摘要 |
A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.
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申请公布号 |
US2005235186(A1) |
申请公布日期 |
2005.10.20 |
申请号 |
US20050151258 |
申请日期 |
2005.06.14 |
申请人 |
SYNTEST TECHNOLOGIES, INC. |
发明人 |
WANG LAUNG-TERNG;LIN MENG-CHYI;WEN XIAOQING;WANG HSIN-PO;HSU CHI-CHAN;KAO SHIH-CHIA;HSU FEI-SHENG |
分类号 |
G01R31/317;G01R31/3185;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/317 |
代理机构 |
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地址 |
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