| 摘要 |
A ferroelectric random access memory (FeRAM) which can embody a high integration cell by sharing a plate line in sub cell array block units is provided. In a read operation mode, the FeRAM stores read data from a cell array block in a timing data register array unit through a common data bus unit, and in a write operation mode, the FeRAM stores read data stored in the timing data register array unit or data inputted from a timing data buffer unit in the cell array block through the common data bus unit.
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