| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem that a manufacturing margin is small and when the distance between source/drain wiring is made short, yield is lowered, in the conventional manufacturing method wherein the number of manufacturing steps is reduced by forming a semiconductor layer and source/drain wiring of a channel etching type and insulating gate type transistor are formed in one photo etching step using a halftone exposure technique. SOLUTION: A four mask process plan by which the halftone exposure technique is not needed is constructed by removing a gate insulating layer when the region of the channel etching type and insulating gate type semiconductor layer is formed to reduce a contact forming step in addition to the rationalization that scanning lines and pseudo pixel electrodes consisting of a laminated layer of a transparent conductive layer and a metallic layer are simultaneously formed, the metallic layer on the false pixel electrodes is removed when aperture parts to a passivation insulating layer are formed and transparent conductive pixel electrodes are formed. COPYRIGHT: (C)2006,JPO&NCIPI |
