发明名称 Post ECP multi-step anneal/H2 treatment to reduce film impurity
摘要 A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm<SUP>2 </SUP>current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H<SUB>2 </SUB>plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm<SUP>2 </SUP>current density and second deposition step at a 60 mA/cm<SUP>2 </SUP>current density is used to deposit a second copper layer-that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.
申请公布号 US2005227479(A1) 申请公布日期 2005.10.13
申请号 US20040812729 申请日期 2004.03.30
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING CO. 发明人 FENG HSIEN-PING;TSAO JUNG-CHIH;CHENG HSI-KUEI;LEE CHIH-TSUNG;CHENG MING-YUAN;LIN STEVEN;CHUANG RAY;LIU CHI-WEN
分类号 H01L21/311;H01L21/768;(IPC1-7):H01L21/311 主分类号 H01L21/311
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