| 摘要 |
<P>PROBLEM TO BE SOLVED: To shorten the lockup time by reducing reference spurious radiation of a PLL synthesizer. <P>SOLUTION: The frequency of a signal inputted to a main counter 12 and a swallow counter 11 is halved by inserting a half fixed frequency divider 10 to the post-stage of a prescaler 9. An (A) value and an (N) value are halved and operated. At that time, the (A) value or the (N) value can not be operated when it is an odd number. Therefore, both of the rising edge and the falling edge of the output of the half fixed frequency divider 10 are counted. The frequency of the signal inputted to the main counter 12 and the swallow counter 11 is halved even when the (A) value or the (N) value is an odd number. Digital noise generated from a counter circuit 25 can be reduced without changing a frequency division ratio of a variable frequency divider 13. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
