PLL ARCHITECTURE HAVING HIGH CONFIGURATION CAPABILITY FOR PROGRAMMABLE LOGIC

摘要

PROBLEM TO BE SOLVED: To provide a clock distributing circuit with a high degree of adaptability by generating a plurality of clocks and outputting them according to programmable selection.

SOLUTION: By inputting a reference signal, a plurality of output clock signals having different frequencies and phases are generated in a phase-locked loop (PLL) circuitry, Each output clock signal is multiplexed for use as an external clock according to arbitrary programmable selection by a multiplexer 228.

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