Receiver and method having full signal path differential offset cancellation capabilities

摘要

There is described a receiver (20) which first comprises an analogue input amplifier (17), a sample and hold differential circuit (22), and two stages of differential comparators that are connected in series, wherein the first stage consists of two comparators (23a,23b) and the second stage of one comparator (15). By properly activating the switches with signals generated by dedicated control logic, the input differential signal is sampled in the sample and hold circuit to generate first and second differential signals. The first differential signal holds a first state and the second differential signal propagates the second state. As result, the signal output by the second comparator stage reflects the differential offset minus the offset compensation. This signal is processed in a successive approximation register (SAR) and the offset compensation value is computed through successive iterations until convergence, digitized and then stored therein. This binary value is applied to a DAC (16) that is connected to the comparators of the first stage for offset compensation.