Circuit arrangement for setting a voltage supply for a test mode of an integrated memory

摘要

A circuit arrangement for setting a voltage supply for a test mode of an integrated memory contains a voltage generator circuit for generating a supply voltage to apply to bit lines of the memory. A control circuit is driven by a test mode signal for identifying a test mode and is connected to the voltage generator circuit. The control circuit enables the supply voltage to be applied to at least one of the bit lines in the test mode. The voltage generator circuit generates a negative supply voltage value in the test mode in order to carry out a burn-in test mode with a sufficiently high voltage difference between word line and bit line even in the case of small feature dimensions and at the same time to comply with voltage limits with regard to a snapback breakdown.