发明名称 |
Delay apparatus and method |
摘要 |
A delay apparatus delays a rising edge and a falling edge of a digital signal. The delay apparatus includes a first edge detection circuit which detects a first edge or rising edge of the digital signal and generates a detection signal; a set circuit that includes a first counter for generating a count value and clearing the count value in response to the detection signal, wherein the set circuit generates a set signal if the count value reaches the number of the reference clock signals corresponding to the delay period of time; a reset circuit which generates a reset signal if an elapsed period of time since a generation of the set signal equals a period of time the digital signal maintains the second logic level; and an output circuit that outputs a delayed digital signal including edges synchronized with the set signal and the reset signal.
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申请公布号 |
US6950486(B2) |
申请公布日期 |
2005.09.27 |
申请号 |
US20010808941 |
申请日期 |
2001.03.16 |
申请人 |
OKI ELECTRIC INDUSTRY CO., LTD. |
发明人 |
ARAKI SATORU |
分类号 |
H03K5/00;H03K5/135;(IPC1-7):H04L7/02 |
主分类号 |
H03K5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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