发明名称 |
Current selective D flip-flop circuit |
摘要 |
An embodiment of a current selective D flip-flop circuit comprises a D flip-flop, a current selector and a current multiplier is disclosed. The current selector is used for receiving and summing at least two currents to form a summed current and having a current comparator for comparing the summed current with one of the at least two currents and selecting one of the at least two currents as an output current. The output current is steered through the current multiplier for biasing the D flip-flop.
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申请公布号 |
US2005206424(A1) |
申请公布日期 |
2005.09.22 |
申请号 |
US20040801455 |
申请日期 |
2004.03.16 |
申请人 |
AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH |
发明人 |
DAJUN YE;PIEW YOONG CHEE;SIONG SIEW YONG |
分类号 |
H03B19/00;H03K3/012;H03K3/2885;H03K3/289;H03K17/041;(IPC1-7):H03B19/00 |
主分类号 |
H03B19/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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