发明名称 CMOS CIRCUIT USING DOUBLE INSULATED GATE FIELD EFFECT TRANSISTOR
摘要 <P>PROBLEM TO BE SOLVED: To provide a CMOS circuit made of a four-terminal double insulated gate field effect transistor in which current of a P type insulated gate field effect transistor and current of an N type insulated gate field effect transistor are made to be the same and in addition, power consumption in a circuit unit when in an unused or standby state is reduced. <P>SOLUTION: Two gate electrodes of a P type four-terminal double insulated gate field effect transistor are electrically connected, further electrically connected to one gate electrode of an N type four-terminal double insulated gate field effect transistor to provide an input terminal of a CMOS inverter circuit, and the potential of the other gate electrode of the N type four-terminal double insulated gate field effect transistor is controlled to thereby control a threshold voltage of the N type four-terminal double insulated gate field effect transistor. <P>COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005260607(A) 申请公布日期 2005.09.22
申请号 JP20040069789 申请日期 2004.03.11
申请人 NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL & TECHNOLOGY 发明人 SEKIKAWA TOSHIHIRO;KOIKE HANPEI;YANAGI EIKUN;MASAHARA MEISHOKU
分类号 G11C11/41;G11C11/412;H01L21/8238;H01L21/8244;H01L27/092;H01L27/11;H01L29/76;H03K19/0948 主分类号 G11C11/41
代理机构 代理人
主权项
地址