发明名称 |
Phase frequency detector with programmable minimum pulse width |
摘要 |
A structure and associated method for reducing a static phase error in a phase-locked loop circuit. The phase-locked loop circuit comprises a voltage controlled oscillator and a phase frequency detector. The voltage controlled oscillator is adapted to provide a first clock signal comprising a first frequency. The phase frequency detector is adapted to compare the first clock signal comprising the first frequency to a reference clock signal comprising a reference frequency. The phase frequency detector comprises a programmable circuit adapted to vary a minimum pulse width of an increment pulse and a minimum pulse width of a decrement pulse. The programmable circuit is further adapted to reduce a static phase error of the phase locked-loop circuit.
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申请公布号 |
US6946887(B2) |
申请公布日期 |
2005.09.20 |
申请号 |
US20030707178 |
申请日期 |
2003.11.25 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
HO SHIU C. |
分类号 |
H03L7/089;(IPC1-7):H03L7/06 |
主分类号 |
H03L7/089 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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