发明名称 |
WAFER LEVEL BURN IN ALIGNMENT DEVICE AND METHOD |
摘要 |
PROBLEM TO BE SOLVED: To laminate a wafer electrode and a contact by facilitating alignment of the wafer electrode and a contact probe stably over a long term even in a production process employing a large number of inspection boards and a large number of alignment devices when inspection of wafers is conducted in a block. SOLUTION: When inspection of the wafers in a lump is conducted by adjusting the parallelism and absolute height with respect to a semiconductor wafer 1 using a parallelism adjusting screw 27 provided on an inspection board 5, laminating of the wafer electrode and the contact can be carried out by facilitating alignment of the wafer electrode and the contact probe stably over a long term even in a production process employing a large number of inspection boards 5 and a large number of alignment devices when inspection of the wafers is conducted in a block. COPYRIGHT: (C)2005,JPO&NCIPI
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申请公布号 |
JP2005251813(A) |
申请公布日期 |
2005.09.15 |
申请号 |
JP20040056954 |
申请日期 |
2004.03.02 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
YAMADA KENJI |
分类号 |
G01R31/30;H01L21/66;(IPC1-7):H01L21/66 |
主分类号 |
G01R31/30 |
代理机构 |
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地址 |
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