| 摘要 |
PROBLEM TO BE SOLVED: To provide a function of reporting a layout portion exceeding an allowable current value by using wiring and contacts on a layout pattern as verification objects in regard to an allowable current value of a semiconductor integrated circuit. SOLUTION: The layout verification device is provided with a layout pattern input means, a layout circuit forming means for forming a layout circuit from the layout pattern, a wiring figure recognizing means for extracting a wiring width, a contact area, and layout coordinations from the layout pattern, an allowable current calculating means for calculating an allowable current from a maximum allowable current density value, the wiring width, and the contact area, a determination element inserting means for inserting a determination element wherein the calculated allowable current value is defined in the layout circuit, an allowable current determining means for executing a circuit simulation to determine whether the allowable current value of the determination element is exceeded during circuit operation, and an error output means for reporting layout coordinates and a current value that was an error in regard to a determination element determined to be an error by the allowable current determining means. COPYRIGHT: (C)2005,JPO&NCIPI
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