| 摘要 |
<p>There are provided a PLL circuit and an information reproduction device capable of reducing the effect of an erroneous detection of a frequency comparator if it does occur and realizing a stable and high-speed frequency pull-in. The PLL circuit includes: a frequency comparator (25) for acquiring a zero cross signal ZC in synchronization with clock CLKA to C by a VCO (23) and observing from which phase to which phase the edge of the zero cross has changed in synchronization with the clock CLKA so as to detect the frequency level as a frequency error and output an up signal UP and a down signal DOWN; an integration circuit (26) for integrating the signal UP or the DOWN; a comparator (27) for receiving the integrated up signal UP or down signal DOWN, judging the direction of the frequency error, and outputting three signals: UPM, DOWNM, NONM; and a gain adjustment circuit (28) for judging whether to output a signal and deciding a feedback gain from the time series pattern of the signals UPM, DOWNM, and NONM.</p> |
