发明名称 |
Delay circuit, testing apparatus, and capacitor |
摘要 |
A delay circuit having an adjustable delay resolution is provided. The delay circuit has a path through which a signal transmits, a field effect transistor whose source region and drain region are connected to the path, and an impressed voltage control unit which controls a voltage to be impressed to the gate electrode of the field effect transistor. The impressed voltage control unit may be a digital analog converter.
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申请公布号 |
US6944835(B2) |
申请公布日期 |
2005.09.13 |
申请号 |
US20030413344 |
申请日期 |
2003.04.14 |
申请人 |
ADVANTEST CORP. |
发明人 |
OKAYASU TOSHIYUKI |
分类号 |
G01R31/28;G01R31/30;H03K5/00;H03K5/13;(IPC1-7):G06F17/50;H03H11/26 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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