| 摘要 |
A novel row and column pre-decoding scheme for semiconductor memories is disclosed. The address lines are translated to a special code where for every address combination, k of m bits are at Logic High. This coding slightly increases the number of address lines, but allows a simpler decoding scheme where the complements of the address lines are not needed for the decoding. Thus the number of global address lines in the decoder decreases sharply, along with the total number of transistors. The result is smaller size, less power and faster operation. |
