| 摘要 |
A semiconductor memory device having a shared sense amplifier architecture includes a bitline equalizing voltage generator, which recycles a boost voltage to generate bitline equalizing voltage. The bitline equalizing voltage is used to generate signals for activating bitline equalizing circuits to precharge the bitlines of at least one of the first and second memory block with a bitline precharge voltage, when the memory block is not currently selected for a data operation. The bitline equalizing voltage generator may be configured to recycle the boost voltage that was used to generate a bitline isolation signal or a wordline drive signal.
|
