| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To prevent an operation mode setting circuit from being erroneously shifted to a test mode just after power supply. <P>SOLUTION: An operation mode setting signal is inputted by each bit from input terminals IN1 to IN4, and mode bits 0 and 1 are inputted to latch circuits LC1 and LC2, and mode bits 2 and 3 are inputted to latch circuits LC3 and LC4, and outputted synchronously with a clock CLK, and the mode bits 0 and 2 are inputted as they are, and the mode bits 1 and 3 are inverted and inputted to an AND circuit AD1, and outputted after AND arithmetic operation is performed. Just after power supply, possibility that "1" or "0" is all outputted from the latch circuits LC1 to LC4 is high, and they are complementarily inverted by inverters IV3 and IV4 so that it is possible to surely discriminate outputs when "1" or "0" are not all outputted, and that it is possible to prevent the error of operation mode setting. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
