发明名称 |
Method for compensation of the shortening of line ends during the formation of lines on a wafer |
摘要 |
In order to compensate for the shortening of line ends ( 30 ) in a circuit design of an integrated circuit, in a first step, hammerheads or serifs ( 50 ) are attached to the line ends ( 30 ) by means of rule-based OPC corrections. The line ends modified in this way are revised further by downstream application of a simulation-based OPC correction before mask or direct wafer writer data are calculated. As a result of the formation of the pattern revised by the simulation-based correction on the wafer, there actually arises in an approximate manner owing to the proximity effects the layout created by the rule-based correction with the supplemented line ends ( 30 ) on the wafer.
|
申请公布号 |
US2005196686(A1) |
申请公布日期 |
2005.09.08 |
申请号 |
US20050066734 |
申请日期 |
2005.02.25 |
申请人 |
MEYER DIRK;HENKEL THOMAS;THIELE JORG;KECK MARTIN |
发明人 |
MEYER DIRK;HENKEL THOMAS;THIELE JORG;KECK MARTIN |
分类号 |
G03F7/20;G03F9/00;(IPC1-7):G03F9/00 |
主分类号 |
G03F7/20 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|