发明名称 |
Method of designing semiconductor integrated circuit, designing apparatus, and inspection apparatus |
摘要 |
A method of designing a semiconductor integrated circuit, comprises: replacing a circuit element disposed in the semiconductor integrated circuit with a transistor having a high threshold value or a circuit element having a small juxtaposition number in order to prevent deviation of a signal voltage flowing through the semiconductor integrated circuit from a power voltage and a ground voltage; replacing a circuit element disposed in a subsequent stage of the replaced circuit element in order to prevent the deviation of the signal voltage from the power voltage and the ground voltage from being propagated to a subsequent stage with a transistor having a high threshold value or a circuit element having a small juxtaposition number; and then arranging circuit elements constituting the semiconductor integrated circuit in such a manner that the semiconductor integrated circuit stably operates.
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申请公布号 |
US2005198594(A1) |
申请公布日期 |
2005.09.08 |
申请号 |
US20050057205 |
申请日期 |
2005.02.15 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
ITAKA YASUHITO |
分类号 |
G06F17/50;H01L21/82;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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