| 发明名称 |
Method and apparatus for handling cyclic buffer access |
| 摘要 |
A first logical memory address identifies a first logical memory location that is outside of a logical buffer space. The first logical memory address is received and is translated into a second logical memory address that identifies a second logical memory location that is within the logical buffer space.
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| 申请公布号 |
US6941441(B2) |
申请公布日期 |
2005.09.06 |
| 申请号 |
US20030386768 |
申请日期 |
2003.03.12 |
| 申请人 |
INTEL CORPORATION |
发明人 |
MAOR MOSHE |
| 分类号 |
G06F12/00;G06F12/02;G06F12/10;(IPC1-7):G06F12/10 |
主分类号 |
G06F12/00 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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