| 摘要 |
A digital circuit tolerant of a race condition problem circuit includes a sense amplifier receiving first and second input data and generating first and second sense amplification signals in response to an enable clock signal generated using a clock signal and an enable signal, and a cascode signal latch receiving the first and second sense amplification signals and generating first and second cascode signals. The first and second sense amplification signals or the first and second cascode signals are selectively transmitted by a switch unit as first and second output control signals, respectively, and then output as first and second multiplexer output signals, respectively, by a dynamic multiplexer in response to a predetermined selection signal.
|
