| 摘要 |
An apparatus and method for converting a dual-rail input. The apparatus combines two useful operand bits and two auxiliary operand bits so that, in a data mode, two output operands of three output operands have a value which is different from that of the third output operand. In a preparation mode, the three output operands of the apparatus have the same value. The apparatus and method may preferably be employed in a three-operands adder as an interface between a dual-rail three-bits half adder and a sum-carry stage of a two-bits full adder so to achieve the same level of security as a full implementation of the three-operands adder in dual-rail technology, despite the two-bits full adder being implemented in single-rail technology.
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