发明名称 |
Method and apparatus for designing circuits using high-level synthesis |
摘要 |
A method for performing high-level synthesis (HLS) of a digital design includes a first phase for performing transformations on a behavioral description of the design, and a second phase for selecting a transformation from a plurality of transformations for transforming the behavioral description. The method further includes a third phase for implementing the transformed behavioral description using lower level primitives, and a fourth phase for generating implementation codes for the design.
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申请公布号 |
US2005193359(A1) |
申请公布日期 |
2005.09.01 |
申请号 |
US20050057416 |
申请日期 |
2005.02.14 |
申请人 |
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA |
发明人 |
GUPTA RAJESH K.;GUPTA SUMIT;DUTT NIKIL;NICOLAU ALEXANDRU |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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