HIGH VOLTAGE AND LOW ON-RESISTANCE LDMOS TRANSISTOR HAVING EQUALIZED CAPACITANCE
摘要
A high voltage LDMOS transistor according to the present invention includes P-field blocks in the extended drain region of a N-well. The P-field blocks form the junction-fields in the N-well for equalizing the capacitance of parasitic capacitors between the drain region and the source region and fully deplete the drift region before breakdown occurs. A higher breakdown voltage is therefore achieved and the N-well having a higher doping density is thus allowed. The higher doping density reduces the on-resistance of the transistor. Furthermore, the portion of the N-well generated beneath the source diffusion region produces a low-impedance path for the source region, which restricts the transistor current flow in between the drain region and the source region.
申请公布号
WO2005081322(A1)
申请公布日期
2005.09.01
申请号
WO2004CN00732
申请日期
2004.07.02
申请人
SYSTEM GENERAL CORP.;HUANG, CHIH-FENG;YANG, TA-YUNG;LIN, JENN-YU G.;CHIEN, TUO-HSIN