| 摘要 |
PROBLEM TO BE SOLVED: To provide a designing method, or the like of a semiconductor integrated circuit capable of facilitating the automatic arrangement of data signal wiring. SOLUTION: There are provided a cell library recorder 4 for recording a cell library including a plurality of cells, where a clock signal input end or a clock signal output end is provided in a third metal layer or a fourth metal layer, or a data signal input end or a data signal output end is provided in one of first-fourth metal layers; a cell arrangement section 5; a clock signal wiring arrangement section 6 for arranging clock signal wiring in the third or fourth metal layer; and a data signal wiring arrangement section 7 for arranging data signal wiring in one of the first-fourth metal layers. COPYRIGHT: (C)2005,JPO&NCIPI
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