| 摘要 |
PROBLEM TO BE SOLVED: To provide a processor, and to further provide technology for speeding up processing therein. SOLUTION: By providing a bus switch 145 allowing connection switching to a plurality of memory buses provided in each memory allowing individual access, and a bus switch controller 144 capable of controlling operation of the bus switch according to a memory access request from a central processor 10 or a data buffer controller 142, and allowing connection to the plurality of memory buses 15-1 to 15-n provided in each the image memory allowing the individual access, the access to the image memories 16-1 to 16-n can be individually performed through a corresponding memory bus. Thereby, probability of competition of the memory access is reduced, and the image processing is speeded up. COPYRIGHT: (C)2005,JPO&NCIPI
|
