A CMOS level converter with a gated output to reduce power consumption in following circuits and in the converter itself

摘要

The output of a CMOS level converter is at a high logic level when a control signal "PC control" is asserted. This ensures that following circuits receive a good logic level even when the power supply to the circuit providing the input " V IN" is turned off or is being turned off or on. The provision of a good logic level to following circuits helps to reduce power consumption in those circuits. NMOS transistor 106 ensures that no current can flow in transistor 105 when the control signal is asserted. The high output level at N2 ensures that no current can flow in transistor 104 when the control signal is asserted, because PMOS transistor 101 is disabled. A similar circuit with a low output when the control signal is asserted is described (figure 2).