发明名称 |
Redundancy circuit and semiconductor device using the same |
摘要 |
A redundancy control circuit includes a redundancy decoder and a decoder killer circuit. The redundancy decoder includes a plurality of fuse circuits corresponding to a plurality of determination signals which are previously activated, and each of the plurality of fuse circuits contains a plurality of fuse sections each containing a fuse. The decoder killer circuit generates a killer signal when at least one of the plurality of determination signals is active, and the killer signal is outputted to an external unit in a first check mode. One of the plurality of fuse circuits is selected and determination signals corresponding to non-selected fuse circuits are inactivated. A specific fuse section of the selected fuse circuit inactivates the determination signal to provide indication of whether the fuse section is cut.
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申请公布号 |
US6930935(B2) |
申请公布日期 |
2005.08.16 |
申请号 |
US20040770422 |
申请日期 |
2004.02.04 |
申请人 |
ELPIDA MEMORY INC. |
发明人 |
NANBA YASUHIRO;WATANABE HIROSHI |
分类号 |
G11C29/04;G11C7/00;G11C11/401;G11C29/00;G11C29/02;(IPC1-7):G11C7/00 |
主分类号 |
G11C29/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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