| 摘要 |
A delay circuit comprising first and second transistors (Ml, M2), the gate of each of which being coupled to the input (or "PRE") signal. The drain of the second transistor (M2) is connected to the supply voltage VDD and its source is coupling to the drain of the first transistor (M1). A third transistor (MO) is provided, the input signal (PRE) being coupled to its gate via an inverter (10). The drain of transistor (MO) is connected at a point between the source of transistor (M2) and the drain of transistor (M I), and the source of transistor (MO) is connected to ground. A capacitor (CO) is connected between the source of transistor (M1) and ground, and a buffer (20) is provided at the output (TIMER). The function of this arrangement is to propagate with delay the transitions from the PRE signal to the TIMER signal. The rising transition is propagated very fast, the speed of propagation being equal to the charging time of capacitor (CO) through the two conducting transistors (M1, M2). The falling transition, on the other hand, is propagated with a large delay as it is equal to the charging time of the capacitor through a conducting transistor (MO) and a transistor in sub-threshold (Ml). |
