发明名称 Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor
摘要 The present invention provides a method and apparatus for controlling a processing priority assigned alternately to a first thread and a second thread in a multithreaded processor to prevent deadlock and livelock problems between the first thread and the second thread. In one embodiment, the processing priority is initially assigned to the first thread for a first duration. It is then determined whether the first duration has expired in a given processing cycle. If the first duration has expired, the processing priority is assigned to the second thread for a second duration.
申请公布号 US6928647(B2) 申请公布日期 2005.08.09
申请号 US20030365918 申请日期 2003.02.13
申请人 INTEL CORPORATION 发明人 SAGER DAVID J.
分类号 G06F9/48;(IPC1-7):G06F15/16 主分类号 G06F9/48
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