| 摘要 |
A semiconductor device-testing apparatus which is capable of testing semiconductor devices simultaneously by a simple construction. A plurality of latch circuits latch output signals outputted from a plurality of DUTs having the same test signal "test" inputted thereto. A P-S conversion circuit sequentially outputs an expected value signal "exp", which is an expected value of signals that the DUTs should output in response to the test signal "test", and a plurality of latched signals, for a latch time period. An encoder circuit compares the latched signals with the expected value signal "exp". A memory stores the latched signals and the expected value signal "exp" delivered from the P-S conversion circuit, when the latched signals do not agree with the expected value signal "exp". A determination circuit determines the quality of each of the DUTs, based on the latched signals and the expected value signal "exp" stored in the memory.
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