| 摘要 |
A flash memory 1 based on the multilevel storage technology for storing the information of two or more bits is provided with four banks 2 a to 2 d. For example, in the left side of the bank 2 a, a data latch 6 a is provided along one short side of the bank 2 a, while in the right side thereof, a data latch 6 b is provided along the other short side of the bank 2 a. At the lower side of the data latches 6 a , 6 b, arithmetic circuits 7 a , 7 b are provided. The data latches 6 a , 6 b are respectively formed of SRAMs. A sense latch 5 a is divided to one half in the right and left directions with reference to the center of sense latch row. The divided sense latch 5 a is connected with the data latches 6 a , 6 b via the signal lines respectively allocated along both short sides of the bank 2 a.
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