| 摘要 |
PROBLEM TO BE SOLVED: To provide a main row decoder of a semiconductor memory device which detects the state change of the least significant bit of the main row decoder and makes a main word line active or free-charged only when the state of the least significant bit changes. SOLUTION: The main row decoder includes: a bank controller for generating an internal RAS signal in response to an active and precharge signal; a first pulse generator for generating a first pulse signal when the internal RAS signal transitions, a second pulse generator for generating a second pulse signal when the internal RAS signal or self refresh signal transitions; an address latch circuit for latching the least significant bit of a row address in response to the first pulse signal; and a row pre-decoder for decoding outputs of the address latch circuit in response to the second pulse signal. COPYRIGHT: (C)2005,JPO&NCIPI
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