Optimal mapping of LUT based FPGA

摘要

A method and system for improved optimal mapping of LUT based FPGA's. The invention comprises performing a topological sort on the network to be mapped, whereby the network is represented in form of a Directed Acyclic Graph. The system locates feasible reconvergent paths existing from transitive fan-ins of each node using a Reconvergent Path Locator for replicating fan-outs of the nodes in the DAG, and therefore optimizing the number of LUT's and the time consumed in the mapping process.