| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem that it is difficult to suppress an increase in power comsumption, although it is effective to reduce clock pulse width in order to maintain the hold time restrictions at the time of a test mode, in the register corresponding to a scan using a pulse trigger type latch. SOLUTION: A pulse generation circuit 1 is so constituted to generate a pulse signal PCK with small width when scanning a control signal NT is L level (during a test mode), and to generate a pulse signal PCK with large width when a scanning control signal NT is H level (during a normal operation mode). In such a way that the width of pulse signal PCK input into a latch circuit 13 is made small at the time of a test mode, and made large at the time of a normal operation mode, while maintaining the hold time restrictions at the time of a test mode, the setup time restrictions at the time of a normal operation mode can be made to ease, the equivalent working speed can be attained with lower supply voltage, and accordingly the power consumption can be reduced. COPYRIGHT: (C)2005,JPO&NCIPI
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